I am a Lecturer (~Assistant Professor) in Computer Science at Newcastle University, United Kingdom, based within the Secure and Resilient Systems group. Prior to this, I was a Senior Research Fellow at the Smart Card Centre (SCC) within the Information Security Group (ISG) at Royal Holloway, University of London.
My expertise lies trusted execution environments and hardware-assisted security more generally; side-channel and fault injection attacks; boot-time security; and smart cards, secure elements (e.g. SIM cards) and their applications. I'm also an active member of the Linux and RISC-V communities, serving the latter on the security subcommittee and the TEE working group.
If you are interested in pursuing a project, Ph.D. etc. on the above topics, then please reach out using the email address below.
Before my current post at Newcastle University, I was funded at Royal Holloway through the EU Horizon 2020 EXFILES, unifying European law enforcement agencies, the private sector, and academia to develop novel data extraction and mobile security circumvention techniques. Examples include microarchitectural side-channels and fault injections against TEEs, full-disk encryption, and secure boot sequences on mobile devices.
Before academia, I worked in fintech at Atom Bank, the UK's first mobile bank; and at OneSpan, a NASDAQ-listed cybersecurity vendor, working as a research scientist developing new product offerings and enhancements.
I hold a Ph.D. in Information Security from the Information Security Group at Royal Holloway, University of London, and a B.Sc. in Computer Science from Newcastle University.
My technical publications can be found on my Publications page or on Google Scholar. Recent highlights include the discovery of design-level security vulnerabilities on all known sensor-enabled Android devices.
Our project, Chameleon, has been funded by EPSRC. Here, we're tying CPU execution to environmental attributes. I'll shortly be recruiting for a research associate position.
I've been provided hardware prototypes through the UK Digital Security by Design (DSBD) initiative and ARM Morello programme to evaluate the CHERI architecture. I'm happy to hear from prospective students who wish to join these efforts and work on some interesting CHERI projects.
Our work on recognising black-box functions using hardware performance counters (HPCs) was accepted to IEEE Transactions on Computers, a top-tier journal in computer hardware. We show that HPCs on mainstream processors can be used as a side-channel for vulnerability detection (using OpenSSL as a use case), interrogating trusted execution environments (using OP-TEE and ARM TrustZone), and general function fingerprinting with high accuracy. The paper can be viewed here.
We comprehensively show that combining modalities, e.g. L1 cache hits, TLB misses, branch mis-predictions and more, is far more powerful than using individual ones explored up to this point. Personally, it's reasonable to expect that multi-modal micro-architectural attacks will be a source of major security problems; far more than, say, Spectre-style speculative execution or cache attacks alone.
I am serving on the Programme Committee of IFIP SEC 2024.
I am also a regularly invited reviewer for many leading journals on the topics of TEEs and hardware and mobile security, including: